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15–14
Table 15–20. DSP Block Parameters
Chapter 15: Arithmetic Library
Name
Output Saturation
Operation Type
Use Output Overflow Port
Register Data Inputs to the
Multiplier(s)
Register Output of the
Multiplier
Register Output of the
Adder
Register Chainout Adder
Register Shiftout
Use Enable Port
Use User Asynchronous
Clear Port
OR Asynchronous Clear
Input with Global Aclr
Value
None (wrap),
Symmetric,
Asymmetric
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or off
Description
You can disable (wrap), or enable saturation. Symmetric saturation
specifies that the absolute value of the maximum negative number is
equal to the maximum positive number. Asymmetric saturation specifies
that the absolute value of the maximum negative number is 1 greater than
the maximum positive number. Do not enable rounding unless you have
enabled saturation.
Turn on to use the overflow output for the saturation unit.
Turn on to create registers at the data inputs to the multiplier. (Always on
if in shiftin mode.)
Turn on to create a register at the data output from the multiplier.
Turn on to create a register at the output of the adder. (Always on if
accumulator mode is enabled.)
Turn on to create a register at the output of the chainout adder (if it is
used).
Registers the shiftouta output (if it is used).
Turn on to use the clock enable input ( ena ) if using registers.
Turn on to use the asynchronous clear input ( aclr ) if using registers.
This parameter turns on, if you enable User Asyncrounous Clear input
(aclr) . If parameter value is on, the user asynchrounous clear signal is
ORed with global clear signal before it is used. If off, global clear is
ignored, and only user clear is used.
The default value for the parameter is on (as DSP Builder does reset
ORing by default for all blocks).
1
Compilation in the Quartus II software requires that the input bit widths are 18 bits
when you use the chainout adder input, output rounding with an output LSB in the
range 6 to 21, or output saturation with an output MSB in the range 28 to 43.
Table 15–21 shows the DSP block I/O formats.
Table 15–21. DSP Block I/O Formats
(1)
I/O
Simulink
(2) , (3)
VHDL
Type
(4)
I1[ L1].[R1]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I
….
In [L1].[R1]
I(n+1) [1]
I(n+2) [1]
….
In: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I(n+1): in STD_LOGIC
I(n+2): in STD_LOGIC
Explicit
...
Explicit
where 3 < n < 9
DSP Builder Handbook
where 3 < n < 9
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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